This invention relates generally to interconnect structures for integrated circuits, and more specifically to fabrication methods and resulting structures for skip vias formed between non-adjacent multilevel metallization layers in a semiconductor device.
In fabricating semiconductor devices, multiple electrical connections are typically formed to each device, and millions of devices can be on a substrate. Openings filled with a conductive material are typically formed to connect the device connections to higher device levels for eventual connection to the electrical package contacts. With shrinking device sizes, the pitches between these electrical vias have also been shrinking.
Vias can typically be formed through dielectric layers, for example, interlayer dielectrics, to metallized layers and to components of the actual devices. The electrical connections between devices on the substrate and from the package contacts to the devices can be routed through the different metallized layers, which can act as wiring (e.g., channels). The multiple levels of interconnecting wiring are typically separated by the intervening dielectric layers through which the vias are formed. In typical integrated circuit packages, seven or more metallization levels could be involved. The layout of the electrical connections can therefore be incredibly complex. Multiple patterning techniques involving registered mask patterns can be used to form the different levels. Multiple cycles of masking and etching can be used. This is typically considered the back-end-of-line (BEOL) fabrication stage.
With ever decreasing device dimensions, forming the individual components and electrical contacts becomes more difficult. An approach is therefore needed that retains the positive aspects of traditional field effect transistor (FET) structures, while overcoming the scaling issues created by forming smaller device components and the interconnects.